以Verilog實作五階管線化CPU，取指、指令解碼、執行、存取記憶體、回寫，實現16道MIPS指令。透過建構算術邏輯單元、控制單元、位移器、多工器、乘法器、計數器等元件，完成算術運算、邏輯運算、資料搬移與分支跳躍指令。搭配暫存器與控制訊號，同時利用無操作指令與危障控制，避免資料發生衝突，確保正確傳遞。

Implemented a five-stage pipelined CPU in Verilog, including instruction fetch, decode, execute, memory access, and write-back stages, supporting 16 MIPS instructions. Designed and integrated components such as an ALU, control unit, shifter, multiplexer, multiplier, and counters to execute arithmetic, logic, data transfer, and branch instructions. Used registers and control signals, along with no-op instructions and hazard management, to prevent data conflicts and ensure correct instruction flow.